1. Technical Field
The present invention generally relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits capable of reducing the effect of skew across a plurality of chips therein.
2. Related Art
FIG. 1 is a block diagram of a conventional semiconductor integrated circuit. As illustrated in FIG. 1, a conventional semiconductor integrated circuit 1 may include a plurality of chips CHIP0 through CHIPn.
The plurality of chips CHIP0 through CHIPn may all be configured in the same manner. The plurality of chips CHIP0 through CHIPn may commonly receive an external voltage VDD and an external clock signal CLK from outside the plurality of chips CHIP0 through CHIPn.
One chip CHIP0 of the plurality of chips CHIP0 through CHIPn may include a clock buffer 11 and a plurality of circuit blocks BLK0 to BLKm.
The clock buffer 11 may receive the external clock signal CLK to generate an internal clock signal ICLK which may be suitably used in the chip.
The plurality of circuit blocks BLK0 through BLKm may receive the external voltage VDD and the internal clock signal ICLK to perform predetermined functions.
The plurality of chips CHIP0 through CHIPn may be implemented as chips that are manufactured by a semiconductor process and determined to be good products through a test. In this case, the respective chips may be manufactured by different manufacturing processes, and a skew may exist between the chips manufactured by different manufacturing processes. That is, the chips may have different signal delay characteristics.
However, the plurality of circuit blocks BLK0 through BLKm are operated in accordance with the same external voltage VDD, even though the signal delay characteristics thereof are different from each other.
Therefore, when any one of a plurality of chips included in a semiconductor integrated circuit is manufactured by a different process, a skew may occur. The skew may cause an operation error in the semiconductor integrated circuit.